Abstract:

       This paper presented a novel digital delay system based on such positives as high conversion rate, low delay and high reliability of emitter coupled logic (ECL).The LVTTL signal,which was the output of FPGA and served as the input trigger signal, was transmitted to AD9500 after level conversion. The delayed output signal of AD9500 was converted back to LVTTL signal to be the ouput signal of the system terminal. Differential signal served as the input of the system, and terminal circuit was employed to process the transmitted signal. Test results show that the system achieves a delay resolution of 100 ps.

Key words: digital delay, emitter coupled logic, AD9500