SHANDONG SCIENCE ›› 2016, Vol. 29 ›› Issue (2): 96-100.doi: 10.3976/j.issn.1002-4026.2016.02.018

• Other Research Article • Previous Articles     Next Articles

Design of a parallel signed multiplyaccumulator

ZHANG Lin1,TIAN Xianzhong1,2,ZHAO Xingwen1,YAN Guang1,GE Zhaobin1   

  1. 1. Institute of Automation, Shandong Academy of Sciences, Jinan 271018, China;
    2. School of Instrumentation & Electrical Engineering, Jilin University, Changchun 130026, China
  • Received:2015-06-11 Published:2016-04-20 Online:2016-04-20

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Abstract:

We employ complement distributed algorithm to simplify addition, subtraction and multiplication of signed number, unsigned number and the number with mixed symbols. We further design a new multiplyaccumulator structure through improving tree structure of an accumulator and logic circuit of a full adder. It is implemented with EP1C3T144C8 device from Altera company. Its effectiveness is proved through multiplyaccumulating functionality and timing simulation result of six ninebit signed operands. Its design overcomes the negatives of large RAM resource occupancy and no coefficient update of conventional distributed algorithm (DA). It can therefore be applied to the design of digital filters, and digital signal processors (DSP) as a rapid compute unit.

Key words: multiplyaccumulator, signednumber, variable coefficient

CLC Number: 

  • TN431.2

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