基于射极耦合逻辑的数字延迟系统

J4 ›› 2011, Vol. 24 ›› Issue (5): 22-25.

基于射极耦合逻辑的数字延迟系统

王忠民, 赵鑫, 王丰贵, 张延波, 杨传法, 张琳

山东省科学院自动化研究所，山东济南 250014

收稿日期:2011-05-23 出版日期:2011-10-20 发布日期:2011-10-20
通信作者: 王忠民（1981-），男，硕士，主要从事超宽带信号产生和高速数字电路设计等方面的研究。 E-mail:lifenet@yeah.net

An emitter coupled logic based digital delay system

WANG Zhong-Min, ZHAO Xin, WANG Feng-Gui, ZHANG Yan-Bo, YANG Chuan-Fa, ZHANG Lin

Institute of Automation, Shandong Academy of Sciences, Jinan 250014, China

Received:2011-05-23 Online:2011-10-20 Published:2011-10-20

摘要/Abstract

摘要：

利用射极耦合逻辑(ECL)转换速度快、延迟小、可靠性强等特点，提出了一种新颖的数字延迟系统实现方案。现场可编程门阵列(FPGA)输出的LVTTL电平信号作为系统的输入触发信号，经过电平转换传输给8位数字可编程延迟芯片AD9500。AD9500的延迟输出再经过电平转换，以LVTTL电平信号作为系统终端的输出形式。在信号传输过程中，系统采用差分方式，并对传输信号做了端接处理，增强了高速信号的抗干扰性。测试结果显示系统实现了分辨率为100 ps的数字延迟。

关键词: 数字延迟, 射极耦合逻辑, AD9500

Abstract:

This paper presented a novel digital delay system based on such positives as high conversion rate, low delay and high reliability of emitter coupled logic (ECL).The LVTTL signal,which was the output of FPGA and served as the input trigger signal, was transmitted to AD9500 after level conversion. The delayed output signal of AD9500 was converted back to LVTTL signal to be the ouput signal of the system terminal. Differential signal served as the input of the system, and terminal circuit was employed to process the transmitted signal. Test results show that the system achieves a delay resolution of 100 ps.

Key words: digital delay, emitter coupled logic, AD9500

中图分类号:

TN79⁺1

王忠民, 赵鑫, 王丰贵, 张延波, 杨传法, 张琳. 基于射极耦合逻辑的数字延迟系统[J]. J4, 2011, 24(5): 22-25.

WANG Zhong-Min, ZHAO Xin, WANG Feng-Gui, ZHANG Yan-Bo, YANG Chuan-Fa, ZHANG Lin. An emitter coupled logic based digital delay system[J]. J4, 2011, 24(5): 22-25.